View RS2051_4140155.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Page No. : 1/13
RS2051
Novel Low Cost Green-Mode PWM Controller with Soft Start & Latch Mode
Description
The RS2051 is a highly integrated low cost current mode PWM controller, which is ideal for small power current mode of offline AC-DC fly-back converter applications. Making use of external resistors, the IC changes the operating frequency and automatically enters the PFM/CRM (Cycle Reset Mode) under light-load/zero-load conditions. This can minimize standby power consumption and achieve power-saving functions. With a very low start-up current, the RS2051 could use a large value start-up resistor (2Mohms). Built-in synchronized slope compensation enhances the stability of the system and avoids sub-harmonic oscillation. Dynamic peak current limiting circuit minimizes output power change caused by delay time of the system over a universal AC input range. Leading edge blanking circuit on current sense input could remove the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. Cycle-byCycle current limiting ensures safe operation even during short-circuit. Excellent EMI performance is achieved built-in soft start with 1.2mSsoft driver and frequency jitter. The RS2051 offers perfect protection like OVP(Over Voltage Protection)OLP(Over Load Protection)SCP(Short circuit protection)OTPSense Fault Protection LM (Latch Mode) and OCP(Over current protection). The RS2051's output driver is soft clamped to maximum 16.5V to protect the power MOSFET. RS2051 is offered in SOT-23-6L, SOT-8 and DIP-8 packages.
Features
Low Cost, PWM&PFM&CRM (Cycle Reset Mode) Low Start-up Current (about 1.5A) Low Operating Current (about 2.2mA) Current Mode Operation Under Voltage Lockout (UVLO) Built-in Synchronized Slope Compensation Built-in fixed soft start with 1.2mS Built-in Frequency jitter for better EMI Signature Programmable PWM Frequency Audio Noise Free Operation Leading edge Blanking on Sense input Constant output power limiting for universal AC input Range SOT-23-6LSOP8 and DIP-8 Pb-Free Packaging Compatible with SG6848 (6849) / SG5701 / SG5848 / LD7535 (7550) / OB2262 (2263) / OB22782279 Soft Clamped GATE output voltage 16.5V VDD over voltage protect 25.6V Cycle-by-cycle current limiting Sense Fault Protect ion OTP (Over Temperature Protection) Output SCP (Short circuit Protection) Output OLP (Over Load Protection) Latch mode After OLP&SCP High-Voltage CMOS Process with ESD
Applications
Switching AC/DC Adaptor Battery Charger Open Frame Switching Power Supply Standby Power Supplies Set-Top Box Power Supplies 384X Replacement
Pin Configurations
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 2/13
Name GND FB RI SEN VDD GATE
Description GND Pin Voltage feedback pin. Output current of this pin could controls the PWM duty cycleOLP and SCP. This pin is to program the switching frequency. By connecting a resistor to ground to set the switching frequency Current sense pin, connect to sense the MOSFET current Supply voltage pin Totem output to drive the external Power MOSFET.
Typical Application Circuit
Block Diagram
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 3/13
Absolute Maximum Ratings
Symbol VDD IOVP VFB VSEN PD ESD Parameter Supply voltage Pin Voltage VDD OVP maximal enter current Input Voltage to FB Pin Input Voltage to SEN Pin Power Dissipation ESD Capability, HBM Model ESD Capability, Machine Model Lead Temperature (Soldering) 20second: SOT-23-6L 10second: DIP-8 10second: SOP-8 Rating 40 20 -0.3 to 6V -0.3 to 6V 300 2500 250 220 260 230 -55 to + 150 Unit V mA V V mW V V
TL
TSTG
Storage Temperature Range
RECOMMENDED OPERATION CONDITION
Symbol VDD RI TOA PO FPWM Parameter VDD Supply Voltage RI PIN Resistor Value Operation Ambient Temperature Output Power Frequency of PWM Min ~ Max 11~20 65~130 -20~85 0~80 30~150 Unit V K ohm W KHz
Electrical Characteristics (Ta=25C unless otherwise noted, VDD = 15V.)
Symbol IST ISS VDDON VDDOFF VDCLAMP VDDAIS TSS TOFF TRESTART IFB VFB IFB_0D IPFM ICRM VPFM VCRM IOLP&SCP VOLP&SCP TOLP&SCP VTH_L VTH_H TPD RCS VSCP TSCP FOSC DS-RS2051-02 Parameter Startup Current Operating Current Turn-on Threshold Voltage Turn-off Threshold Voltage VDD Clamp Voltage Anti Intermission Surge VDD Voltage Soft start Time Over temperature Protection Temperature restart VFB=0V VFB=3V VFB=Open IVDD=20mA Conditions Min. Supply Voltage (VDD Pin) Typ. 1.5 3.2 2.2 1.65 12.8 7.8 25.6 12.7 1.2 130 100 1.57 4.6 1.47 1.37 1.45 0.51 0.30 152 4.2 50 0.65 0.85 150 50 177 1.2 60 65 Max. Unit A mA mA mA V V V V mS mA V mA mA mA V V uA V mS V V ns K mV mS KHz www.Orister.com
Voltage Feedback (FB Pin) Short Circuit Current VFB=0V Open Loop Voltage VFB=Open Zero Duty Cycle FB current Enter PFM&PWM, FB current Enter CRM, FB current PFM Threshold VFB Enter CRM Threshold VFB Enter OLP&SCP FB current Enter OLP&SCP FB voltage OLP&SCP min. delay Time RI=100K 33 Current Sensing (SEN Pin) Minimum Voltage Lever Maximum Voltage Lever Delay to Output Input Impedance Sense short protect voltage Sen. short protect Delay Time Oscillator (RI Pin) Normal Frequency RI=100Kohm 55 September, 2007
Page No. : 4/13
FPFM DCMAX_W DCMAX_F FTEMP TBLANK FJITTER VOL VOH TR1 TF1 TR2 TF2 TR3 TF3 TR4 TF4 VGCLAMP
PFM Frequency RI=100Kohm Maximum Duty Cycle PWM RI=100Kohm Maximum Duty Cycle PFM RI=100Kohm -30-85 Frequency Temp. Stability Leading-Edge Blanking Time Frequency jitter RI=100Kohm -4 GATE Drive Output (GATE Pin) Output Low Level VDD=15V, IO=20mA Output High Level VDD=15V, IO=20mA 9 Rising Time CL=500pF Falling Time CL=500pF Rising Time CL=1000pF Falling Time CL=1000pF Rising Time CL=1500pF Falling Time CL=1500pF Rising Time CL=2000pF Falling Time CL=2000pF Output Clamp Voltage VDD=20V
22 77 14 5 300 4 0.8 123 71 248 116 343 153 508 209 16.5
KHZ % % % nS % V V ns ns ns ns ns ns ns ns V
Notice: The drive current of GATE pin is a variable value, which is decided by
I = K (VVDD - VGATE - 2.8) 2 (Among these, K is a invariable coefficientVGATE is the voltage of GATE pin, VVDD is
the voltage of VDD pin)So the higher the VDD voltage is and the lower the output voltage is, the bigger the drive transient current is. When the GATE voltage is 0V and the VDD voltage is 13V, the output drive current would over 120mA. The output driver current would decrease with increasing of the GATE voltage.
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 5/13
OPERATION DESCRIPTION
Current Mode
Compared to voltage mode control, current mode control has a current feedback loop. When the voltage of the Sense resistor peak current of the primary winding reaches the internal setting value VTH, the register resets and the power MOSFET cuts off. So, to detect and modulate the peak current cycle-by-cycle could control the output of the power supply. The current feedback has a good linear modulation rate and a fast input and output dynamic impact, and avoid the pole that the output filter inductance brings and the two-class system descends to the one-class. So it widens the frequency range and optimizes overload protection and short circuit protection.
Startup Current and Under Voltage Lockout
The startup current of RS2051 is set to be very low so that a large value startup resistor can be used to minimize the power loss. For AC to DC adaptor with universal input range design, a 2 M, 1/8 W startup resistor and a 10uF/25V VDD hold capacitor could be used. The turn-on and turn-off threshold of the RS2051 is designed to 12.8V/7.8V. During startup, the hold-up capacitor must be charge to 12.8V through the startup resistor. The hysteresis is implemented to prevent the shutdown from the voltage dip during startup.
Internal Bias and OSC Operation
A resistor connected between RI pin and GND pin sets the internal constant current source to charge or discharge the internal fixed capacitor. The charge time and discharge time determines the internal clock speed and the switching frequency. Increasing the resistance will reduce the value of the input current and reduce the switching frequency. The relationship between RI and PWM switching frequency follows the below equation within the RI allowed range.
FOSC =
6000 (kHz ) RI ( K)
For example, a 100k resistor RI could generate a 13uA constant current and a 60kHz PWM switching frequency. The suggested operating frequency range of RS2051 is within 30KHz to 150KHz.
Green Power Operation
The power dissipation of switching mode power supply is very important in zero load or light load condition. The major dissipation results from conduction lossswitching loss and consume of the control circuit. However, all of them relates to the switching frequency. There are many difference topologies has been implemented in different chip. The basic operation theory of all these approaches intends to reduce the switching frequency under light-load or no-load condition. The RS2051s green power function adapts PWMPFM and CRM combining modulation. When RI resistor is 100k, the PWM frequency is 60kHz in medium or heavy load operation. Through modifying the pulse width, The RS2051 could control output voltage. The current of FB pin increases when the load is in light condition and the internal mode controller enters PFM&PWM when the feedback current is over 1.37mA. The operation frequency of oscillator is to descend gradually. When the feedback current is over 1.43mA, the frequency of oscillator is invariable, namely 22kHz. To decrease the standby consumption of the power supply, Chip-Rail introduces the Cycle Reset Mode technology (CRM). If the feedback current is over 1.45mA, mode controller of the RS2051 would reset internal register all the time and cut off the GATE pin. While the output voltage is lower than the set value, the register would be set, the GATE pin operate again. So the frequency of the internal OSC is invariable, the register would reset some pulses so that the practical frequency is decreased at the GATE pin.
RS2051 Green-Power Function
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 6/13
Internal Synchronized Slop Compensation
Although there are more advantages of the current mode control than conventional voltage mode control, there are still several drawbacks of peak-sensing current-mode converter, especially the open loop instability when it operates in higher than 50% of the duty-cycle. To solve this problem, the RS2051 is introduced an internal slope compensation adding voltage ramp to the current sense input voltage for PWM generation. It improves the close loop stability greatly at CCM, prevents the sub-harmonic oscillation and thus reduces the output ripple voltage.
VSLOP = 0.33 x
DUTY = 0.4389 x DUTY DUTYMAX
Slop Compensation
Current Sensing & Dynamic peak limiting
The current flowing by the power MOSFET comes into being a voltage VSENSE on the Sense pin cycle-by-cycle, which compares to the internal reference voltage, and controls the reverse of the internal register, limits the peak current IMAX of the primary of
1 2 x L x I MAX . So adjusting the RSENSE can set the maximal output power of 2 VIN the power supple. The current flowing by the power MOSFET has an extra value ( I = x TD ) due to the system delay LP
the transformer. The transformer energy is
E=
time that is from detecting the current through the Sense pin to power MOSFET off in the RS2051 (Among these, VIN is the primary winding voltage of the transformer and LP is the primary wind inductance). VIN ranges from 85VAC to 264VAC. To guarantee the output power is a constant for universal input AC voltage, there is a dynamic peak limit circuit to compensate the system delay T that the system delay brings on.
IPEAK MAX = IPEAK MAX
Soft Start
0.65V (VIN = 264V ) RSENSE 0.85V = (VIN = 85V ) RSENSE
The RS2051 features an internal soft start during the initial power on. As soon as VDD reaches ON, the voltage on the internal fixed capacitor is gradually increased from zero up to the maximum internal clamping level. The time of the soft start is fixed about 1.2mS for the constant charge current and the fixed capacitor.
Frequency Jitter
The frequency jittering is introduced in the RS2051. As following figure, the internal oscillation frequency is modulated by itself. A whole surge cycle includes 8 pulses and the jittering ranges from -4% to +4%. Thus, the function could minimize the electromagnetic interferer from the power supply module.
Frequency Jitter
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 7/13
OLP&SCP
To protect the circuit from being damaged under the over load or short circuit condition, a smart OLP&SCP function is implemented in the RS2051. When short circuit or over load occurs in the output end, the feedback cycle would enhance the voltage of FB pin, while the voltage is over 4.2V or the current from FB is below 152uA, the internal detective circuit would send a signal to shut down the GATE and pull down the VDD voltage, then the circuit is restart. To avoid the wrong operation when circuit starts, the delay time is set. When the RI resistance is 100Kohm, the delay time TOLP&SCP is between 33mS and 50mS. The relationship between RI and TOLP&SCP follows the below equation.
RI x 2 RI x 3 (mS ) < TOLP & SCP < (mS ) 3 6 x 10 6 x 10 3
Over Temperature Protection
The RS2051 has a built-in temperature sensing circuit to shut down PWM output once the junction temperature exceeds 130C. While PWM output is shut down, VDD voltage will gradually drop to the UVLO voltage, and VDD voltage will gradually increase again. If the junction temperature is still higher than 130C, the PWM controller will be shut down again. This situation will continue until the temperature drops below 100C. The PWM output will then be turned back. The temperature hysteresis window for the OTP circuit is 30C.
Sense Fault Detect
Changing the resistance of Sense pin could limit the maximal peak current of power MOSFET. If the Sense pin is short circuit to the ground and the RS2051 is overload, the power MOSFET and transformer is easy to be shattered. So, the short circuit protection is built in the RS2051. Every time to start up, the circuit would detect the voltage of the Sense pin when the start signal is send. If the voltage keeps lower than 177mV, the circuit would be cut off and restart in 1.2mS. But, when the switch power is cut off, there could always be a big noise on the ground, so to achieve this function, it is strongly suggested that the board on the ground of the sense pin must be attention.
Anti Intermission Surge
When the power supplies change the heavy load to light load immediately, there could be tow phenomena caused by system delay. They are output voltage overshot and intermission surge. To avoid it, the anti intermission surge is built in the RS2051. If it occurs, the FB current is to increase rapidly, the GATE would be cut off for a while, VDD pin voltage descends gradually. When VDD reaches 12.7V, the GATE pin would operate again, which the frequency is 22KHz and the max. Duty cycle is 14%.
Leading-edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the Sense pin, which would disturb the internal signal from the sampling of the RSENSE. There is a 300nS leading edge blanking time built in to avoid the effect of the turn-on spike, and the power MOSFET cannot be switched off during the moment. So that the conventional external RC filtering on sense input is no longer required.
Over Voltage Protection (OVP)
There is a 25.6V over-voltage protection circuit in the RS2051 to improve the credibility and extend the life of the chip. When the VDD voltage is over 25.6V, the GATE pin is to shutdown immediately and the VDD voltage is to descend rapidly.
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 8/13
Latch Mode
In some applications, latch operation for SCP&OLP may be necessary. The RS2051 offer this function. When the output is OLP or SCP, the RS2051 could cut off GATE output and pull down VDD voltage immediately, and enter Latch Mode. To restart the power supply, it is necessary to disconnect the AC line voltage of the power supply.
GATE Driver & Soft Clamped
The RS2051' output designs a totem pole to drive a periphery power MOSFET. The dead time is introduced to minimize the transfixion current during the output operating. The novel soft clamp technology is introduced to protect the periphery power MOSFET from breaking down and current saturation of the Zener.
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 9/13
PACKAGE DEMENSIONS
DIP-8L
Dimensions
Symbol A A1 A2 b b1 D E E1 e L eB Millimeters Min. 0.381 3.175 Typ. Max. 5.334 3.429 Min. 0.015 0.125 Inches Typ. Max. 0.210 0.135
9.017 6.223 2.921 8.509 0
3.302 1.524 0.457 9.271 7.620 6.350 2.540 3.302 9.017 7
10.160 6.477 3.810 9.525 15
0.355 0.245 0.115 0.335 0
0.130 0.060 0.018 0.365 0.300 0.250 0.100 0.130 0.355 7
0.400 0.255 0.150 0.375 15
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 10/13
SOP-8L
Dimensions
Symbol A A1 b c D E e F H L Millimeters Min. 1.346 0.101 0.406 0.203 4.648 3.810 1.016 5.791 0.406 0 4.978 3.987 1.524 6.197 1.270 8 0.183 0.150 0.040 0.228 0.016 0 Typ. Max. 1.752 0.254 Min. 0.053 0.004 0.016 0.008 0.196 0.157 0.060 0.244 0.050 8 Inches Typ. Max. 0.069 0.010
1.270 0.381X45
0.050 0.015X45
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 11/13
SOT-23-6L
Dimensions
Symbol A A1 B b C D e H L Millimeters Min. 0.700 0.000 1.397 0.300 2.591 2.692 0.838 0.080 0.300 Max. 1.000 0.100 1.803 0.559 3.000 3.099 1.041 0.254 0.610 Min. 0.028 0.000 0.055 0.012 0.102 0.106 0.033 0.003 0.012 Inches Max. 0.039 0.004 0.071 0.022 0.118 0.122 0.041 0.010 0.024
Ordering Information
PART NUMBER RS2051S RS2051P RS2051N PIN-PACKAGE SOP-8L DIP-8L SOT-23-6L
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 12/13
Soldering Methods for Orister's Products
1. Storage environment: Temperature=10oC~35oC Humidity=65%15% 2. Reflow soldering of surface-mount devices Figure 1: Temperature profile
tP TP Ramp-up TL Tsmax Temperature tL Critical Zone TL to TP
Tsmin tS Preheat
Ramp-down
25
t 25oC to Peak Time
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Tsmax to TL - Ramp-up Rate Time maintained above: - Temperature (TL) - Time (tL) Peak Temperature (TP) Time within 5oC of actual Peak Temperature (tP) Ramp-down Rate Time 25oC to Peak Temperature 3. Flow (wave) soldering (solder dipping) Products Pb devices. Pb-Free devices.
Sn-Pb Eutectic Assembly <3oC/sec 100oC 150oC 60~120 sec <3oC/sec 183oC 60~150 sec 240oC +0/-5oC 10~30 sec <6oC/sec <6 minutes
Pb-Free Assembly <3oC/sec 150oC 200oC 60~180 sec <3oC/sec 217oC 60~150 sec 260oC +0/-5oC 20~40 sec <6oC/sec <8 minutes
Peak temperature 245 C 5 C 260 C +0/-5 C
o o o o
Dipping time 5sec 1sec 5sec 1sec
DS-RS2051-02
September, 2007
www.Orister.com
Page No. : 13/13
Important Notice:
* All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of Orister Corporation. * Orister Corporation reserves the right to make changes to its products without notice. * Orister Corporation products are not warranted to be suitable for use in Life-Support Applications, or systems. * Orister Corporation assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
DS-RS2051-02
September, 2007
www.Orister.com

▲Up To Search▲

Price & Availability of RS2051

	To Download RS2051 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .